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mcu332
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332equ.arc
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332SIM.EQU
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1990-03-12
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****************************************************************************
* $RCSfile: 332sim.equ $
* $Revision: 1.1 $
* $Date: 90/03/12 13:45:42 $
*
* -------------------------------------------------------------
* Module Name: 332SIM - MC68332 SIM Registers
* -------------------------------------------------------------
*
* Description:
* 1. This file contains EQUates for all the System Integration
* Module (SIM) registers and bits for the MC68332. Consult
* the "MC68332 System Integration Module User's Manual", part
* number SIM32UM/AD, for more details.
* 2. A 128-byte address space is reserved for the SIM, though not
* all are used.
* 3. The ABSOLUTE address area where the register array block
* appears in memory is specified by the value of REG$, which
* should be defined in the user's system definitions. The
* value of REG$ is $YFF000, where Y = M111 and M reflects the
* modmap bit (MM) in the module configuration register (MCR).
*
* REG$ value Comments
* ---------- ---------------------------------
* $007FF000 MCR MM bit = 0
* $00FFF000 MCR MM bit = 1 (reset default)
* $FFFFF000 MCR MM bit = 1 (reset default)
* Forces short addressing (unused
* upper address lines are ignored)
* 4. The following pages summarize these registers and their
* associated addresses.
*
* Notes:
* 1. Motorola reserves the right to make changes to this file.
* Although this file has been carefully reviewed and is
* believed to be reliable, Motorola does not assume any
* liability arising out of its use. This code may be freely
* used and/or modified at no cost or obligation to the user.
* 2. All descriptions are WORD values unless stated otherwise.
* 3. The DEF macro along with the BIT$CODE symbol controls the
* actual bit definitions. See the DEF macro in the DEF.MAC
* file for details.
* 4. This file was made for use with the Motorola Development
* Systems M68000 Family Structured Assembler for MS-DOS,
* known as M68MASM.
* 5. To use this file, either use an INCLUDE statement or just
* merge this file into your source code file. Consult your
* assembler's user's manual for the details specific to your
* situation. Reference the code segment example below for
* usage ideas (shown in M68MASM for MS-DOS syntax).
*
* REG$ EQU $FFFFF000 Register base address
* * NOTE: A31-24 unused in MC68332, so we set them all =1
* * in order to use absolute short addressing mode!
* NOLIST
* INCLUDE "DEF.MAC"
* INCLUDE "332SIM.EQU"
* LIST
* START CLR SIM$+SIMTR Absolute addressing!
* LEA SIM$,A6 . OR
* CLR (SIMTR,A6) Indexed addressing!
* * Bit number usage w/indexing!
* BCLR.B #MM,(MCR+1,A6)
* OR.W (1<<.FRZBM)+(1<<.FRZSW),(MCR,A6)
* * Bit value usage w/indexing!
* AND.B #(-_MM-1)&$FF,(MCR+1,A6)
* OR.W _FRZBM+_FRZSW,(MCR,A6)
* * Bit field usage w/indexing!
* MOVE.B #(5*PIRQL_)+(66*PIV_),(PICR,A6)
* * Bit field mask usage w/indexing!
* MOVE.W (PICR,A6),D0
* MOVE.W D0,D1
* AND.W #PIRQL_MSK,D0 Isolate PIRQL field
* MOVE.L #.PIRQL,D2
* LSR.W D2,d0 and right justify it!
* AND.W #PIRQL_NMSK,D1 Clear PIRQL field.
*
* For bit fields, a value (0-N) will be placed inside. As
* can be seen in the last line above, this is accomplished
* by multiplying the bit field label by the desired value
* for the field. This line initializes the PICR register
* which has two bit fields, PIRQL_ and PIV_. These fields
* are initialized to interrupt level 5 and vector 66
* respectively, by this line (places a value of $0542 into
* the PICR register).
* 6. Be careful when using any of the BIT instructions (BCHG,
* BCLR, BSET, BTST), as they will only operate on a BYTE of
* memory, not a WORD. Thus to access a bit in the least
* significant half of a word sized register (B0-B7), "+1"
* must be added to the operand address. See the code
* segment example in item 5 above.
* 7. Because the equate files can generate many listing pages,
* the user may wish to disable the listing via NOLIST and
* LIST directives as seen in the above example code.
* 8. The latest version of this file is maintained on the
* Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-
* 3733). It operates continuously (except for maintenance)
* at 1200-2400 baud, 8-bits, no parity. Download the
* archive file 332EQU.ARC to get all the files.
*
****************************************************************************
*********************************************************************
* Define Module Base Address
*********************************************************************
SIM$ EQU REG$+$A00 SIM base address
*********************************************************************
* Define Registers and Bits
*********************************************************************
MCR EQU $000 Module Configuration Register
DEF EXOFF,B15 . external clock off
DEF FRZSW,B14 . freeze software enable
DEF FRZBM,B13 . freeze bus monitor enable
DEF SLVEN,B11 . slave mode enable
DEF SHEN,B8,2 . show cycle enable (2 bits)
DEF SUPV,B7 . supervisor/unrestricted data space
DEF MM,B6 . module mapping
* NOTE: MM is a WRITE-ONCE field!
DEF IARB,B0,4 . interrupt arbitration (4 bits)
*-------------------------------------------------------------------*
SIMTR EQU $002 System Integration Module Test Register
DEF MASK,B10,6 . mask number (read only) (6 bits)
DEF SOSEL,B6,2 . scan out select (2 bits)
* NOTE: SOSEL bit field is different bit position from TPU's TTCR!
DEF SHIRQ,B4,2 . show interrupt request (2 bits)
DEF FBIT,B2,2 . force bit (2 bits)
DEF BWC,B0,2 . bandwidth control (2 bits)
*-------------------------------------------------------------------*
SYNCR EQU $004 Clock Synthesizer Control Register
* NOTE: M68MASM doesn't allow labels like ".W" and ".X"!
DEF WBIT,B15 . W frequency control bit
DEF XBIT,B14 . X frequency control bit
DEF Y,B8,6 . Y frequency control bits (6 bits)
DEF EDIV,B7 . E-clock divide rate
DEF SLIMP,B4 . limp mode
DEF SLOCK,B3 . synthesizer lock
DEF RSTEN,B2 . reset enable
DEF STSIM,B1 . stop mode system integration clock
DEF STEXT,B0 . stop mode external clock
*-------------------------------------------------------------------*
*UNUSED EQU $006 Unused position (BYTE)
*-------------------------------------------------------------------*
RSR EQU $007 Reset Status Register (BYTE)
* NOTE: RSR is a READ-ONLY register!
DEF EXT,B7 . external reset
DEF POW,B6 . powerup reset
DEF SW,B5 . software watchdog reset
DEF HLT,B4 . halt monitor reset
DEF LOC,B2 . loss of clock reset
DEF SYS,B1 . system reset
DEF TST,B0 . test submodule reset
*-------------------------------------------------------------------*
SIMTRE EQU $008 System Integration Module Test E Register
* NOTE: SIMTRE is a WRITE-ONLY register reserved for Factory Testing!
*-------------------------------------------------------------------*
*UNUSED EQU $00A Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $00C Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $00E Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $010 Unused position (BYTE)
*-------------------------------------------------------------------*
PORTE EQU $011 Port E Data Register (BYTE)
DEF PE7,B7 . port E data bit 7
DEF PE6,B6 . port E data bit 6
DEF PE5,B5 . port E data bit 5
DEF PE4,B4 . port E data bit 4
DEF PE3,B3 . port E data bit 3
DEF PE2,B2 . port E data bit 2
DEF PE1,B1 . port E data bit 1
DEF PE0,B0 . port E data bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $012 Unused position (BYTE)
*-------------------------------------------------------------------*
PORTE1 EQU $013 Port E Data Register 1 (BYTE)
*-------------------------------------------------------------------*
*UNUSED EQU $014 Unused position (BYTE)
*-------------------------------------------------------------------*
DDRE EQU $015 Port E Data Direction Register (BYTE)
DEF DDE7,B7 . port E data direction bit 7
DEF DDE6,B6 . port E data direction bit 6
DEF DDE5,B5 . port E data direction bit 5
DEF DDE4,B4 . port E data direction bit 4
DEF DDE3,B3 . port E data direction bit 3
DEF DDE2,B2 . port E data direction bit 2
DEF DDE1,B1 . port E data direction bit 1
DEF DDE0,B0 . port E data direction bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $016 Unused position (BYTE)
*-------------------------------------------------------------------*
PEPAR EQU $017 Port E Pin Assignment Register (BYTE)
DEF PEPA7,B7 . port E pin assignment bit 7
DEF PEPA6,B6 . port E pin assignment bit 6
DEF PEPA5,B5 . port E pin assignment bit 5
DEF PEPA4,B4 . port E pin assignment bit 4
DEF PEPA3,B3 . port E pin assignment bit 3
DEF PEPA2,B2 . port E pin assignment bit 2
DEF PEPA1,B1 . port E pin assignment bit 1
DEF PEPA0,B0 . port E pin assignment bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $018 Unused position (BYTE)
*-------------------------------------------------------------------*
PORTF EQU $019 Port F Data Register (BYTE)
DEF PF7,B7 . port F data bit 7
DEF PF6,B6 . port F data bit 6
DEF PF5,B5 . port F data bit 5
DEF PF4,B4 . port F data bit 4
DEF PF3,B3 . port F data bit 3
DEF PF2,B2 . port F data bit 2
DEF PF1,B1 . port F data bit 1
DEF PF0,B0 . port F data bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $01A Unused position (BYTE)
*-------------------------------------------------------------------*
PORTF1 EQU $01B Port F Data Register 1 (BYTE)
*-------------------------------------------------------------------*
*UNUSED EQU $01C Unused position (BYTE)
*-------------------------------------------------------------------*
DDRF EQU $01D Port F Data Direction Register (BYTE)
DEF DDF7,B7 . port F data direction bit 7
DEF DDF6,B6 . port F data direction bit 6
DEF DDF5,B5 . port F data direction bit 5
DEF DDF4,B4 . port F data direction bit 4
DEF DDF3,B3 . port F data direction bit 3
DEF DDF2,B2 . port F data direction bit 2
DEF DDF1,B1 . port F data direction bit 1
DEF DDF0,B0 . port F data direction bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $01E Unused position (BYTE)
*-------------------------------------------------------------------*
PFPAR EQU $01F Port F Pin Assignment Register (BYTE)
DEF PFPA7,B7 . port F pin assignment bit 7
DEF PFPA6,B6 . port F pin assignment bit 6
DEF PFPA5,B5 . port F pin assignment bit 5
DEF PFPA4,B4 . port F pin assignment bit 4
DEF PFPA3,B3 . port F pin assignment bit 3
DEF PFPA2,B2 . port F pin assignment bit 2
DEF PFPA1,B1 . port F pin assignment bit 1
DEF PFPA0,B0 . port F pin assignment bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $020 Unused position (BYTE)
*-------------------------------------------------------------------*
SYPCR EQU $021 System Protection Register (BYTE)
* NOTE: SYPCR is a WRITE-ONCE register!
DEF SWE,B7 . software watchdog enable
DEF SWP,B6 . software watchdog prescale
DEF SWT,B4,2,MSK8 . software watchdog timing (2 bits)
DEF HME,B3 . halt monitor enable
DEF BME,B2 . bus monitor external enable
DEF BMT,B0,2,MSK8 . bus monitor timing (2 bits)
*-------------------------------------------------------------------*
PICR EQU $022 Periodic Interrupt Control Register
DEF PIRQL,B8,3 . periodic int. request level (3 bits)
DEF PIV,B0,8 . periodic interrupt vector (8 bits)
*-------------------------------------------------------------------*
PITR EQU $024 Periodic Interrupt Timing Register
DEF PTP,B8 . periodic timer prescaler control
DEF PITM,B0,8 . periodic timer modulus (8 bits)
*-------------------------------------------------------------------*
*UNUSED EQU $026 Unused position (BYTE)
*-------------------------------------------------------------------*
SWSR EQU $027 Software Service Register (BYTE)
* NOTE: SWSR register always reads as zero (0)!
DEF SWSR,B0,8,MSK8 . software watchdog count (8 bits)
*-------------------------------------------------------------------*
*UNUSED EQU $028 Unused position
*-------------------------------------------------------------------*
TSTMSRA EQU $030 Test Module Master Shift Register A
*-------------------------------------------------------------------*
TSTMSRB EQU $032 Test Module Master Shift Register B
*-------------------------------------------------------------------*
TSTSC EQU $034 Test Module Shift Count
*-------------------------------------------------------------------*
TSTRC EQU $036 Test Module Repetition Counter
*-------------------------------------------------------------------*
CREG EQU $038 Test Module Control Register
DEF BUSY,B15 . busy status bit
* NOTE: BUSY is not writable; read only!
DEF TMARM,B14 . test mode armed status bit
DEF COMP,B13 . compare status bit
DEF IMBTST,B12 . intermodule bus test
DEF CPUTR,B11 . CPU test register
DEF QBIT,B10 . quotient bit
DEF MUXEL,B9 . multiplexer select bit
DEF ACUT,B4 . activate circuit under test
* NOTE: ACUT always reads as zero (0)!
DEF SCONT,B3 . start continuous operation
DEF SSHOP,B2 . start shifting operation
DEF SATO,B1 . start automatic test operation
DEF ETM,B0 . enter test mode
* NOTE: ETM is a WRITE-ONCE bit!
*-------------------------------------------------------------------*
DREG EQU $03A Test Module Distributed Register
DEF WAIT,B8,3 . wait counter preset (3 bits)
DEF MSRA18,B7 . master shift reg. A bit 18
DEF MSRA17,B6 . master shift reg. A bit 17
DEF MSRA16,B5 . master shift reg. A bit 16
DEF MSRA,B5,3 . master shift reg. A bits 16-18 (3 bits)
DEF MSRAC,B4 . master shift reg. A configuration
DEF MSRB18,B3 . master shift reg. B bit 18
DEF MSRB17,B2 . master shift reg. B bit 17
DEF MSRB16,B1 . master shift reg. B bit 16
DEF MSRB,B1,3 . master shift reg. B bits 16-18 (3 bits)
DEF MSRBC,B0 . master shift reg. B configuration
*-- Wait Counter Values --*
WAIT$2 EQU 0 Delay 2 system clock cycles
WAIT$4 EQU 1 Delay 4 system clock cycles
WAIT$6 EQU 2 Delay 6 system clock cycles
WAIT$8 EQU 3 Delay 8 system clock cycles
WAIT$10 EQU 4 Delay 10 system clock cycles
WAIT$12 EQU 5 Delay 12 system clock cycles
WAIT$14 EQU 6 Delay 14 system clock cycles
WAIT$16 EQU 7 Delay 16 system clock cycles
*-------------------------------------------------------------------*
*UNUSED EQU $03C Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $03E Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $040 Unused position (BYTE)
*-------------------------------------------------------------------*
PORTC EQU $041 Port C Data Register (BYTE)
DEF PC7,B7 . port C data bit 7
DEF PC6,B6 . port C data bit 6
DEF PC5,B5 . port C data bit 5
DEF PC4,B4 . port C data bit 4
DEF PC3,B3 . port C data bit 3
DEF PC2,B2 . port C data bit 2
DEF PC1,B1 . port C data bit 1
DEF PC0,B0 . port C data bit 0
*-------------------------------------------------------------------*
*UNUSED EQU $042 Unused position
*-------------------------------------------------------------------*
CSPAR0 EQU $044 Chip Select Pin Assignment Register 0
*-------------------------------------------------------------------*
CSPAR1 EQU $046 Chip Select Pin Assignment Register 1
*-------------------------------------------------------------------*
CSBARBT EQU $048 Chip Select Base Address Register Boot
* NOTE: For all CSBARxx registers,
* BITS 15-3= base address field (A23-A11)
* BITS 2-0 = block size field
* See "Chip Select Equates for CSORxx, CSBARxx:" below.
*-------------------------------------------------------------------*
CSORBT EQU $04A Chip Select Option Register Boot
* NOTE: For all CSORxx registers,
* BIT 15 = aysnc/sync mode (MODE)
* BITS 14-13= upper/lower byte option (BYTE)
* BITS 12-11= read/write (R/W)
* BIT 10 = address/data strobe (STRB)
* BITS 9-6 = data strobe acknowledge (DSACK)
* BITS 5-4 = address space (SPACE)
* BITS 3-1 = interrupt priority level (IPL)
* BIT 0 = autovector enable (AVEC)
* See "Chip Select Equates for CSORxx, CSBARxx:" below.
*-------------------------------------------------------------------*
CSBAR0 EQU $04C Chip Select Base Address Register 0
*-------------------------------------------------------------------*
CSOR0 EQU $04E Chip Select Option Register 0
*-------------------------------------------------------------------*
CSBAR1 EQU $050 Chip Select Base Address Register 1
*-------------------------------------------------------------------*
CSOR1 EQU $052 Chip Select Option Register 1
*-------------------------------------------------------------------*
CSBAR2 EQU $054 Chip Select Base Address Register 2
*-------------------------------------------------------------------*
CSOR2 EQU $056 Chip Select Option Register 2
*-------------------------------------------------------------------*
CSBAR3 EQU $058 Chip Select Base Address Register 3
*-------------------------------------------------------------------*
CSOR3 EQU $05A Chip Select Option Register 3
*-------------------------------------------------------------------*
CSBAR4 EQU $05C Chip Select Base Address Register 4
*-------------------------------------------------------------------*
CSOR4 EQU $05E Chip Select Option Register 4
*-------------------------------------------------------------------*
CSBAR5 EQU $060 Chip Select Base Address Register 5
*-------------------------------------------------------------------*
CSOR5 EQU $062 Chip Select Option Register 5
*-------------------------------------------------------------------*
CSBAR6 EQU $064 Chip Select Base Address Register 6
*-------------------------------------------------------------------*
CSOR6 EQU $066 Chip Select Option Register 6
*-------------------------------------------------------------------*
CSBAR7 EQU $068 Chip Select Base Address Register 7
*-------------------------------------------------------------------*
CSOR7 EQU $06A Chip Select Option Register 7
*-------------------------------------------------------------------*
CSBAR8 EQU $06C Chip Select Base Address Register 8
*-------------------------------------------------------------------*
CSOR8 EQU $06E Chip Select Option Register 8
*-------------------------------------------------------------------*
CSBAR9 EQU $070 Chip Select Base Address Register 9
*-------------------------------------------------------------------*
CSOR9 EQU $072 Chip Select Option Register 9
*-------------------------------------------------------------------*
CSBAR10 EQU $074 Chip Select Base Address Register 10
*-------------------------------------------------------------------*
CSOR10 EQU $076 Chip Select Option Register 10
*-------------------------------------------------------------------*
*UNUSED EQU $078 Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $07A Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $07C Unused position
*-------------------------------------------------------------------*
*UNUSED EQU $07E Unused position
*********************************************************************
*
* Chip Select Equates for CSORxx, CSBARxx:
*
CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
CSOR_XX EQU $0000 Reset (unused) value for CSORn
*
B2K EQU 0 2K block size
B8K EQU 1 8K block size
B16K EQU 2 16K block size
B64K EQU 3 64K block size
B128K EQU 4 128K block size
B256K EQU 5 256K block size
B512K EQU 6 512K block size
B1M EQU 7 1MB block size
ASYNC EQU $0000 Asynchronous mode
SYNC EQU $8000 Synchronous mode
CS_UPPB EQU 2*$2000 Upper byte
CS_LOWB EQU 1*$2000 Lower byte
CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
CS_R EQU 1*$800 Read
CS_W EQU 2*$800 Write
CS_RW EQU 3*$800 Read or write
CS_AS EQU 0*$400 Address Strobe (AS*)
CS_DS EQU 1*$400 Data Strobe (DS*)
CS_FAST EQU 14 Fast termination DSACK*
CS_EXT EQU 15 External termination DSACK*
CS_WAIT EQU 1*$40 Wait cycles for DSACK*
CS_CSP EQU 0*$10 CPU space
CS_USP EQU 1*$10 User space
CS_SSP EQU 2*$10 Supervisor space
CS_SUSP EQU 3*$10 Supervisor/User space
CS_LVL EQU 1*$2 Interrupt priority level
CS_AVEC EQU 1 Autovector enable
*********************************************************************
